[Low-Power Cache] Koji Inoue, Tohru Ishihara, and Kazuaki Murakami, "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption,'' Proc. of 1999 International Symposium on Low Power Electronics and Design (ISLPED'99), pp.273-275, Aug. 1999. [DRAM/Logic Integration] Koji Inoue, Koji Kai, and Kazuaki Murakami, "Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs,'' Proc. of The Fifth International Symposium on High-Performance Computer Architecture (HPCA-5), pp.218-222, Jan. 1999. [DRAM/Logic Integration] Koji Inoue, Tohru Ishihara, and Kazuaki Murakami, "High-Performance/Low-Power Cache Architectures for Merged DRAM/Logic LSIs (in Japanese), " IPSJ Journal, Vol. 42, No. 3, 419-431, May 2001. (40th Anniversary Best Paper Award) [Reconfigurable Accelerator]  Hamid. Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, and Maziar Goudarzi, "Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor," The European Event for Electronic System Design & Test (DATE'07), pp.325-330, Apr. 2007. [Performance prediction of Peta-Scale Supercomputers]  R. Susukita, H. Ando, M. Aoyagi, H. Honda, Y. Inadomi, K. Inoue, S. Ishizuki, Y. Kimura, H. Komatsu, M. Kurokawa, K. Murakami, H. Shibamura, S. Yamamura, Y. Yu, "Performance Prediction of Large-scale Parallel System and Application using Macro-level Simulation," International Conference for High Performance Computing, Networking, Storage and Analysis (SC08), Nov. 2008.